1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly relates to a circuit configuration for driving an internal data line. More specifically, the present invention relates to a circuit configuration for accelerating a voltage stress between complementary internal data lines.
2. Description of the Background Art
FIG. 26 is a schematic diagram showing the configurations of a main part of a conventional semiconductor memory device. In FIG. 26, a memory array MA is divided into a plurality of memory sub-blocks MSB. Memory sub-blocks MSB are arranged in alignment in row and column directions. The memory sub-blocks arranged in alignment in the row direction constitute a row block RBK. In FIG. 26, memory array MA is divided into row blocks RBK0 to RBKm along the column direction. In addition, memory sub-blocks MSB arranged in alignment in the column direction constitute a column block CBK. In FIG. 26, memory array MA is divided into column blocks CBK0 to CBKn.
Write/read circuits PW0 to PWn for writing/reading internal data are arranged corresponding to column blocks CBK0 to CBKn, respectively. These write/read circuits PW0 to PWn are connected to an input/output circuit IOK through a data bus DBS having a width of a plurality of bits.
In the semiconductor memory device shown in FIG. 26, data access is made on a column block basis. Among column blocks CBK0 to CBKn, one or a plurality, a predetermined number, of column blocks are simultaneously selected, the write/read circuit(s) arranged corresponding to the selected column block(s) is/are selectively activated and the internal data is written/read to/from the selected column block(s).
In row selection, the selection of a memory cell row is performed on a row block basis. In this row selection, as in the case of the column selection, one or a plurality of row blocks are activated among row blocks RBK0 to RBKn.
FIG. 27 is a schematic diagram showing the configurations of one memory sub-array MSB and associated internal data lines. In FIG. 27, the configuration of a section related to internal data lines transmitting 2-bit internal data is shown by way of example. The bus width of the internal data lines is desirably set.
In FIG. 27, memory sub-array MSB includes a plurality of memory cells MC arranged in a matrix of rows and columns, a plurality of bit lines BL and/BL each connecting to the memory cells in the corresponding column, and a plurality of word lines WL arranged corresponding to the memory cell rows, respectively and to each connecting to the memory cells in the corresponding row. Bit lines BL and/BL are arranged in pairs to transfer complementary data. FIG. 27 representatively shows memory cells MC arranged in two rows and two columns, word lines WLa and WLb arranged corresponding to the memory cells in the two rows, respectively, and bit line pairs BLa, ZBLa and BLb, ZBLb arranged corresponding to the memory cells in the two columns, respectively.
Memory cells MC are arranged corresponding to the crossings between one of the paired bit lines BL and ZBL and word line WL, respectively. In FIG. 27, memory cells MC are arranged corresponding to the crossing between word line WLa and bit line BLa and that between word line WLa and bit line BLb, respectively.
Memory cell MC includes a capacitor MQ which stores information, and an access transistor MT which connects a corresponding capacitor MQ to a corresponding bit line BL or ZBL in accordance with a signal on a corresponding word line WL (which generically represents a word line). Here, bit lines BL and ZBL generically represent bit lines BLa, BLb and ZBLa, ZBLb shown therein, respectively. Access transistor MT consists of an N-channel MOS (insulated gate field effect) transistor.
A sense amplifier SA is arranged corresponding to bit line pair BL and ZBL. When a sense amplifier activation signal SAE is activated, sense amplifier SA is activated to differentially amplify and latch the potentials of corresponding bit line pair BL and ZBL. Sense amplifier SA normally includes a P-sense amplifier which consists of cross-coupled P-channel MOS transistors and an N-sense amplifier which consists of cross-coupled N-channel MOS transistors. Sense amplifier activation signal SAE, therefore, includes a signal which activates the P-sense amplifier and a signal which activates the N-sense amplifier.
A column select gate CSGa which connects bit lines BLa and ZBLa to local data lines LIO0 and ZLIO0, respectively in accordance with a column select signal CSL, is arranged corresponding to bit line pair BLa and ZBLa. Likewise, a column select gate CSGb which is rendered conductive in accordance with column select signal CSL and which connects bit lines BLb and ZBLb to local data lines LIO1 and ZLIO1, respectively, when conductive, is arranged corresponding to bit line pair BLb and ZBLb.
Local data lines LIO0, ZLIO0, LIO1 and ZLIO1 are arranged for each memory sub-block in each column block. In row block selection, local data lines LIO and ZLIO (which generically represent LIO0 and LIO1, and ZLIO0 and ZLIO1, respectively) arranged for the memory sub-blocks in the selected row block are connected to corresponding global data lines described later, respectively.
An equalization transistor LQ0 responsive to a local data line equalization instruction signal LIOEQ is arranged for local data lines LIO0 and ZLIO0. Likewise, an equalization transistor LQ1 responsive to local data line equalization instruction signal LIOEQ is arranged for local data lines LIO1 and ZLIO1. When conductive, equalization transistor LQ0 electrically short-circuits local data lines LIO0 and ZLIO0. When conductive, equalization transistor LQ1 electrically short-circuits local data lines LIO1 and ZLIO1.
Local data lines LIO0, ZLIO0, and LIO1, ZLIO1 are electrically connected to global data lines GIO0, ZGIO0 and GIO1, ZGIO1 through IO select gates IOG0 and IOG1, respectively. IO select gates IOG0 and IOG1 are rendered conductive when IO select signal IOSEL to be activated for a selected row block is activated, and connect, when conductive, corresponding local data lines LIO0, ZLIO0 and LIO1, ZLIO1 to global data lines GIO0, ZGIO0 and GIO1, ZGIO1, respectively.
Global data lines GIO0, ZGIO0 and GIO1, ZGIO1 are arranged in common to the memory sub-blocks included in a column block. In the corresponding column block, one memory row block is selected with respect to global data lines GIO0, ZGIO0, GIO1 and ZGIO1, and the local data lines provided for the memory sub-blocks included in the corresponding row block are electrically connected to the corresponding global data lines.
An equalization transistor GQ0 which electrically equalizes global data lines GIO0 and ZGIO0, and a pull-up circuit PUG0 which pulls up the potentials of global data lines GIO0 and ZGIO0 in data read, are provided for global data lines GIO0 and ZGIO0. Likewise, an equalization transistor GQ1 and a pull-up circuit PUG1 are arranged for global data lines GIO1 and ZGIO1.
Equalization transistors GQ0 and GQ1 become conductive when a global data line equalization instruction signal GIOEQ is activated. When a column block select signal CBS is activated, pull-up circuits PUG0 and PUG1 are activated to pull up the potentials of global data lines GIO, ZGIO0 and GIO1, ZGIO1 to a power supply voltage level, to decrease the voltage amplitudes of global data lines GIO0, ZGIO0 and GIO1, ZGIO1 in data read, to transmit small amplitude read signals and to achieve high speed data read.
In data write, this column block select signal CBS is kept inactive for a selected column block. In accordance with write data, global data lines GIO0, ZGIO0 and GIO1, ZGIO1 are driven to a power supply voltage level and a ground voltage level, respectively.
Global data lines GIO, ZGIO0 and GIO1, ZGIO1 are driven in accordance with the write data by write drivers WRD0 and WRD1, respectively. When a write driver enable signal WDE is activated, write drivers WRD0 and WRD1 generate complementary written data in accordance with data transmitted on data buses DB0 and DB1 of data bus DBS, and drive global data lines GIO, ZGIO0 and GIO1, ZGIO1, respectively. This write driver enable signal WDE is activated only for a selected column block.
FIG. 28 is a signal waveform diagram representing the operation of the semiconductor memory device shown in FIG. 27 in data write. Referring to FIG. 28, the operation of the semiconductor memory device shown in FIG. 27 in data writing will be briefly described.
An array activation signal RACT is driven to an active state in accordance with an external row select operation instruction signal, so that this semiconductor memory device starts a row select operation. When array activation signal RACT is activated, a memory cell row select operation is performed in accordance with an address signal externally applied, word line WL arranged corresponding to an addressed row in the selected row block is driven to a selected state, and the voltage level of selected word line WL rises.
When the voltage level of selected word line WL rises, access transistors MT of memory cells MC connected to selected word line WL turns conductive and the data stored in corresponding capacitors MQ is transmitted to corresponding bit lines BL or ZBL. Bit lines BL and ZBL are kept at intermediate voltage level by a bit line equalization circuit, not shown, in a standby cycle. In accordance with the activation of array activation signal RACT, the equalization operation for bit lines BL and ZBL is stopped. The data stored in the memory cells is read to bit lines BL or ZBL and the other bit lines are kept at precharge voltage level. Accordingly, potential difference between bit lines BL and ZBL is produced in accordance with the data stored in the associated memory cell.
When the potential difference between bit lines BL and ZBL is sufficiently developed, sense amplifier activation signal SAE is activated, the voltages on bit lines BL and ZBL are differentially amplified by a corresponding sense amplifier SA, and bit lines BL and ZBL are driven to power supply voltage Vccs and the ground voltage level in accordance with the read data and the bit line voltages are latched by the associated sense amplifier.
During this row select operation, the circuitry related to the column selection and the write/read of the internal data are kept in a precharged state as in the standby cycle.
In a normal DRAM (dynamic random access memory), a row access instruction for row selection and a column access instruction for column selection and data write/read are applied in a time division multiplexed manner. In a DRAM which has an interface compatible with that of an SRAM (static random access memory), however, a row access instruction and a column access instruction are simultaneously applied by one access instruction and a row select operation and a column select operation are executed internally in a time division multiplexed manner. Therefore, in the above description of the operation of the semiconductor memory device, the row access instruction and the column access instruction may be applied simultaneously and the row select operation and the column select operation may be performed internally in a time division multiplexed manner.
When each sense amplifier completes its sensing operation, a column select operation activation signal CACT is activated in accordance with a column access instruction. When column select operation activation signal CACT is activated, IO select signal IOSEL corresponding to a selected row block turns H level in accordance with the already applied row address signal. In addition, local data line equalization instruction signal LIOEQ becomes L level. As a result, local data lines LIO and ZLIO are connected to global data lines GIO and ZGIO, respectively. Additionally, column block select signal CBS turns L level in accordance with a column block designation address signal included in the column address signal in data writing, whereby the pull-up operations by pull-up circuits PUG0 and PUG1 on global data lines GIO0, ZGIO0 and GIO1, ZGIO1 to power supply voltage Vccs level are stopped.
Then, the write driver enable signal WDE for the selected column block is activated, and write drivers WRD0 and WRD1 drive global data lines GIO0, ZGIO0 and GIO1, ZGIO1 to power supply voltage Vccs and ground voltage levels in accordance with the write data applied through data buses DB0 and DB1, respectively.
The write data applied to global data lines GIO0, ZGIO0 and GIO1, ZGIO1 are transmitted to local data lines LIO0, ZLIO0 and LIO, ZLIO1 through IO select gates IOG0 and IOG1, respectively.
Then, column select signal CSL is driven to a selected state in the form of a one-shot pulse in accordance with the column address signal, so that column select gates CSGa and CSGb are rendered conductive and the data latched by sense amplifiers SA are set at the voltage level according to the write data.
When predetermined time elapses, column related control signals IOSEL, LIOEQ, CSL, CBS, WDE and GIOEQ are each returned to an original precharged state.
In data writing, when column select operation activation signal CACT is activated while column access is made, column select signal CSL is activated only for a short period of time, such as about 4 to 5 ns, and data are written to the selected memory cells.
In data reading, a preamplifier enable signal in place of word driver enable signal WDE is activated to activate a preamplifier circuit, not shown. In data reading, column block select signal CBS is kept at H level, and pull-up circuits PUG0 and PUG1 perform their pull-up operations to decrease the signal amplitudes of the global data lines and transmit read signals at high speed.
The semiconductor memory device is subjected to a stress accelerating test referred to as xe2x80x9cburn-in testxe2x80x9d so as to ensure product reliability. In this stress accelerating test, the semiconductor memory device is operated under conditions of higher voltage and higher temperature than those of the practical usage conditions in an ordinary operation of the semiconductor memory device, a voltage stress and a temperature stress applied to this semiconductor memory device are accelerated and latent defects are thereby made detectable. Such a stress accelerating test is performed on various parts of the semiconductor memory device. One of the items of this stress accelerating test is a data line stress accelerating test.
In this data line stress accelerating test, the voltage stress between local data lines LIO and ZLIO is accelerated and that between global data lines GIO and ZGIO is accelerated. By accelerating the voltage stresses between these complementary data lines, latent short-circuits between the complementary data lines are made revealed. To this end, therefore, it is necessary to transmit a power supply voltage and a ground voltage to one and the other of local data lines LIO and ZLIO, respectively. Likewise, it is necessary to transmit the power supply voltage and the ground voltage to one and the other of global data lines GIO and ZGIO, respectively.
To accelerate the voltage stresses applied to these data lines, conventionally internal write data is transmitted onto global data lines GIO and ZGIO by the write driver, thereby accelerating the stresses between the complementary data lines, i.e., the stress between the global data lines and that between the local data lines.
However, if the write driver is driven while accelerating the stresses between the complementary data lines of the global data lines and the local data lines, the following disadvantage occurs. Specifically, write driver WDR (WDR0, WDR1) is merely activated in accordance with write driver enable signal WDE. Write driver enable signal WDE is activated only for a time period of, e.g., about 3 to 4 ns. Due to this, it is necessary to repeatedly perform a data write operation so as to apply sufficient stresses between the complementary data lines of the global data lines and the local data lines.
To repeatedly perform the data write operation, it is necessary to successively apply a data write instruction externally. In this case, column access instruction may be successively applied with a word line kept in a selected state in accordance with a fast access mode such as a page mode. Normally, however, if one data write instruction is applied, the next data write cannot be instructed for a period referred to generally as a xe2x80x9cCAS precharge periodxe2x80x9d. Further, when a data write instruction is applied, it is necessary to secure setup/hold time for the address signals and the control signals. As a result, data write cycle time become disadvantageously longer, the number of times of repeating the write operations increases so as to sufficiently apply voltage stresses, the stresses cannot be accelerated at high speed, and time required for accelerating the stresses between the complementary data lines becomes disadvantageously longer.
Moreover, if the voltage stresses between the complementary data lines are accelerated using this write driver, the complementary data lines repeat a voltage stress accelerated state and a precharged state alternately. As a result, it is difficult to efficiently apply the stresses between the complementary data lines and the inter-complementary-data-line stress accelerating test time becomes disadvantageously longer.
It is an object of the present invention to provide a semiconductor memory device capable of greatly shortening time required to perform an accelerating test for accelerating the stress between complementary data lines.
It is another object of the present invention to provide a semiconductor memory device capable of efficiently applying a stress between complementary data lines.
A semiconductor memory device according to a first aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of sense amplifiers arranged corresponding to the columns of the memory cells, and sensing and amplifying data of the memory cells in the corresponding columns when activated; a column select control circuit for holding a column select instruction signal in an active state in accordance with a test operation mode instruction signal, and generating the column select instruction signal in the form of a one-shot pulse in accordance with a column access instruction signal in a normal operation mode when the test operation mode instruction signal is deactivated; a column select circuit for connecting a sense amplifier arranged corresponding to a selected column to an internal data bus in response to the column select instruction signal; a write circuit for driving the internal data line in accordance with a write instruction signal; and a write control circuit for holding the write instruction signal in an inactive state when the test operation mode instruction signal is activated.
A semiconductor memory device according to a second aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; an internal data bus for transmitting and receiving data to and from a selected memory cell among the plurality of memory cells; a write circuit for driving the internal data bus in response to a write instruction signal; a write control circuit for holding the write instruction signal in an active state in accordance with a test operation mode instruction signal, and activating the write instruction signal in a one-shot pulse form in response to a write operation mode instruction signal when the test operation mode instruction signal is deactivated; a plurality of sense amplifiers arranged corresponding to the columns of the memory cells, and sensing and amplifying data of the memory cells read to the corresponding columns when activated,; a column select circuit arranged corresponding to the plurality of sense amplifiers, and connecting the sense amplifier arranged corresponding to a selected column to the internal data bus in accordance with a column select signal; and a column select control circuit for holding the column select signal in an inactive state in accordance with the test operation mode instruction signal.
A semiconductor memory device according to a third aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; an internal data bus for transmitting and receiving data to and from a selected memory cell among the plurality of memory cells; a voltage setting circuit selectively activated in accordance with a test operation mode instruction signal, and holding the internal data bus at a predetermined voltage level when activated; and a voltage holding circuit for holding the internal data bus at the predetermined voltage level when an access instruction signal, instructing selection of the selected memory cell, is deactivated while the test operation mode instruction signal is deactivated.
In the test operation mode, complementary data are transmitted to the internal data lines without using the write driver, it is possible to continuously apply a voltage stress between the complementary data lines, it is possible to efficiently accelerate the voltage stress, and it is thereby possible to reduce time required for a complementary data line stress accelerating test. Since the stress voltage is continuously applied to the complementary data lines, it is in particular unnecessary to repeat write operation. In addition, the application/stop of application of the voltage stress are not repeatedly carried out but the voltage stress is efficiently applied between the complementary data lines. It is thereby possible to greatly reduce stress accelerating time.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.